In personal computers, the main system architecture bus provides the means for which subsystems communicate. An example of such a system architecture bus is IBM's Micro Channel Architecture.
In addition, a communications pathway is often needed between a local interface bus and the main system architecture bus. When data is transferred between a subsystem on the main system architecture bus and a device on a local interface bus, it is desirable and sometimes required to use a FIFO memory buffer in the data pathway between the two buses.
The use of a FIFO buffer provides a more capable data flow between the Micro Channel and local interfaces. It achieves this goal by adapting the data rate disparities and decoupling the interactions between the two buses. Furthermore, the FIFO buffer provides for efficient use of the Micro Channel bus by providing the capability of high speed block transfers and reduced arbitration overhead.
To achieve maximum utilization of limited silicon real estate and maximum data transfer performance, the FIFO must be implemented in an efficient and effective manner.